1. FIELD OF THE INVENTION
The invention relates to a circuit configuration for a programmable nonvolatile memory, having a multiplicity of memory cells organized in rows and columns and having a programming circuit, wherein in order to test the memory cells of the memory, the programming circuit contains a test device which applies a programming current in each case to a first predetermined number of memory cells in parallel for a respective first predetermined time period until a first partial programming current of the programming current has been applied to each of the memory cells.
Nonvolatile memories, in particular one time programmable memory circuits (OTP=one time programmable memory), are increasingly being used in integrated microcontroller circuits and the like. Such a memory differs from a customary EPROM only due to the fact that a housing without any windows is used in the course of final assembly, as a result of which it is not possible to erase the memory content through the use of UV light, and consequently the memory can be written to only a single time.
Testing of such a memory therefore takes place prior to final assembly, e.g. while still on the wafer.
However, as the capacity of the memory increases, testing of each memory cell becomes time-consuming since approximately 50 .mu.s are required to write to a memory cell. If the memory has a capacity of e.g. 1 megabit, then a time period of approximately 50 sec per I/O word width would be necessary just to write to each memory cell. Known memories therefore have an additional circuit configuration which allows a plurality of memory cells to be written to in parallel in the test mode. Such memories are disclosed, for example, in Published European Patent Application 0 186 040 A1, corresponding to U.S. Pat. No. 4,742,490 or Published European Patent Application 0 186 051 A2, corresponding to U.S. Pat. No. 4,742,489.
Since the programming current is relatively high as compared with the normal supply current for the component, only a limited number of memory cells can be written to simultaneously. That is because the lines only allow a specific maximum programming current without the module being damaged.